The invention relates to a CMOS technology base cell for the construction of electrical circuits.
The increasing complexity of VLSI electrical circuits makes manual design of the circuit layout increasingly more difficult. The great number of geometric discrete structures of a VLSI circuit forces a transition to automatic layout generation. Given such a layout generating method, the geometric layout structures are acquired from an abstract circuit specification with the assistance of software. The individual layout rectangles are thus dimensioned and placed by means of a program. The particular advantages of a layout generation by software are high flexibility, fast adaptation to new design rules, and short design times.
The overall layout of an electronic circuit is formed from a plurality of such layout rectangles. Given personal design of the electronic circuit, each rectangle is individually dimensioned and individually placed. Given such a method, however, the complexity is not reduced, so that layouts of larger circuits can only be produced with greater expense. The gate-matrix method, on the other hand, reduces the complexity of the circuit design since only certain grid points of a matrix are permitted for placing the geometric structures. According to the gate-matrix principle, layouts having the scope of standard cells are generated and subsequently are further processed with traditional methods. Another method of automatic layout generation is even applicable to extensive VLSI circuits, and reduces the complexity of the circuit design with the assistance of a base cell concept. A layout is constructed to a high degree from parametric base cells. The relative disposition of individual geometric structures to one another is prescribed within a base cell. Further methods for the production of electronic circuits can be derived, for example, from the brochure CAD for VLSI by H. G. Schwartzel, Springer Verlag 1982, for example, pages 63-76, incorporated herein by reference.